1. Field of the Invention
The present invention relates generally to semiconductors and semiconductive devices and more particularly, it relates to PN junctions in such devices which extend at least in part under a protective oxide to a top surface of the bulk semiconductive material. Such junctions are commonly referred to as "planar" junctions, and the technology employed, and the resulting semiconductive devices or circuits, are referred to as "planar". This distinguishes them from so-called "mesa" devices and circuits, wherein whole layers of alternating conductivity type materials are diffused and, by etching to form active devices, the junctions without protective oxide extend only to the edges of the bulk semiconductive material.
Planar devices have heretofore been limited to relatively low voltages because they break down due to certain surface effects at voltages very substantially below the bulk breakdown voltage (BV). Transistors and other planar devices as manufactured under this invention are not limited by such surface breakdown voltages, and are thus capable of higher voltage operation. They are more reliable under normal conditions, since they have a greater margin of safety under equivalent biasing conditions. They may be operated at higher line voltages, eliminating the need for voltage reducing equipment. Alternatively, with surface breakdown eliminated as a problem, geometry can be changed to improve frequency characteristics, or bulk resistivity can be lowered to improve saturation characteristics.
A principal application of the present invention is in the construction of planar transistors, either as discrete devices or as parts of an integrated circuit. Understanding of the invention will be facilitated by briefly reviewing typical prior art procedures for the production of such devices. For the production of an NPN transistor, the starting material will be a wafer of single crystal N-type silicon or a layer of N-type epitaxial silicon grown on a N+type silicon base. The wafer will have a bulk resistivity of several ohm-centimeters (.OMEGA.-cm) and a normal N-type impurity concentration of about 10.sup.14 - 10.sup.15 (concentrations referred to herein, except for starting materials, are surface concentrations, in atoms/cc). After lapping and polishing, or after epitaxial layer depositions, a film of silicon dioxide (SiO.sub.2) is grown on a major surface of the wafer by either low or high temperature oxidation techniques, steam being a common oxidant. For many applications, an oxide film thickness of about 6000 angstroms (A) is sufficient.
The surface geometry of the transistor - more particularly the size and configuration of the base and emitter areas - has been worked out in advance in conformity with desired properties in the finished device, and results in the generation of masks for these areas. Photolithographic techniques are employed, in conjunction with the proper mask, to deposit an etch resist on the entire oxide surface, except the desired base region. Etching through the opening in this mask removes the SiO.sub.2 and exposes the underlying silicon. The wafer is now ready for the steps which will form the base region of the transistor (the body of the wafer will form the N-type collector). The first step is to deposit a controlled amount of P-type material, commonly boron, onto this exposed surface. A diffusion furnace is typically used. For very accurate control of the deposition of the P-type material, it is possible to adjust the deposited concentration by use of a wet oxidation which will serve to leach some of the boron away from the Si and into the SiO.sub.2. By measuring sheet resistance after this step, the desired level of P-type impurities on the silicon surface can be more precisely reached. Other methods are also known.
The next step is to diffuse the P-type material from the surface of the silicon into the body thereof, creating a P-type base region within the N-type collector region. A diffusion furnace is employed for this purpose, and results in a collector-base PN junction being formed between the two regions. The concentration of P-type material in the base region is typically 10.sup.18 - 10.sup.19 atoms per cubic centimeter, and the depth of the diffusion is typically 6 microns. It will be noted that this junction extends up to the single major surface of the wafer around its entire periphery, this being the main characteristic of planar technology.
Formation of the emitter region follows, and involves similar steps. An oxide was grown over the base opening during the base drive-in diffusion and an emitter mask now defines an emitter area within the base area. The oxide in this area is removed by etching, and an N-type material, typically phosphorus, is deposited on the surface and then diffused into it. The concentration of N-type material in the emitter region is typically 10.sup.21 atoms per cc., and the depth of the diffusion is typically 4 microns.
The transistor is now complete except for making electrical contact thereto. Again, the oxide had been regrown over the emitter areas during the emitter diffusion, and yet another mask is now used to define contact areas for the base and emitter terminals. When the oxide has been etched from these areas, a metal such as aluminum is evaporated onto the surface of the wafer. Still another mask is used to cover the desired contact areas, and the metal in the uncovered areas is removed by etching. The collector contact may be on the top or bottom surface. In the latter case, it is formed by evaporating another metal, typically gold onto the bottom surface of the wafer. Normal procedures are to manufacture a large number of these devices on a slice of silicon and, after completing the steps enumerated above, cut or "dice" the slice into individual transistors.
A variety of problems are associated with the point where the lead crosses the junction. These problems are different in different devices and are not well understood, but are generally referred to as channelling, surface inversions, MOS effects and the like. In essence, the voltage in the lead and its polarity induce a change in the behavior of the junction near the surface, which of course changes the behavior of the device. The magnitude of these problems is kept within acceptable limits by spacing the base and emitter contacts sufficiently far apart, and increasing the thickness SiO.sub.2 layer. Increased spacing of the base and emitter, however, requires that the chip itself be larger. This is undesirable since the larger the chip, the fewer chips will be produced per wafer.
The present invention overcomes the lead-over-junction problems in dielectrically isolated semiconductive devices having high-voltage junctions of the above-noted type. Dielectric isolation is a well known technique familiar to those skilled in the art. Briefly, separate discrete devices are produced from a single wafer and are separated from each other by dielectric material, generally SiO.sub.2, and are retained in a matrix of polycrystalline silicon or even glass. To produce such devices, a slice of single crystal silicon is first grooved in a desired pattern to a desired depth to define discrete device areas on each chip. SiO.sub.2 is grown on the entire surface. Polycrystalline silicon is then epitaxially grown on the SiO.sub.2. The slice is then turned over, and the single crystal surface is lapped down until the grooves cut in the other side appear. The resulting slice comprises a plurality of "tubs" of single crystal silicon, each entirely surrounded by a layer of SiO.sub.2 and set in a matrix of polycrystalline silicon. Depending on groove geometry, the tubs may be isolated on the surface by just SiO.sub.2 or SiO.sub.2 and polycrystalline material. Active devices are assembled in the silicon "tubs" and leads are evaporated onto the surface. The polycrystalline surface may be lapped or etched away to expose the tub bottoms for collector electrode attachment, or the collector lead may be on the top surface.
Dielectrically isolated devices may employ the high-voltage double diffusion type junctions referred to hereinabove and they will, ordinarily, be subject to the same lead-over-junction problems that conventional planar devices and circuits suffer from.
Before considering the efforts of prior workers to raise the voltage characteristics of planar devices, the applicable parts of the operation of a conventional planar transistor should be considered, and attention is directed to FIG. 1. This is a typical transistor structure as could be produced by the above-enumerated processing steps. Regions of different conductivity type are labelled (it is to be understood that NPN and PNP structures are substantially equivalent in operation, and either may be employed). Thus the transistor 10 of FIG. 1 comprises an N-type collector region 12, a P-type base 14 and an N-type emitter 16, collector-base junction 18 and emitter-base junction 20 defining the various regions. A layer of SiO.sub.2 22 covers the surface of the device except for the base contact 24 and the emitter contact 26, both of which are typically evaporated aluminum. A gold collector contact 28 is evaporated onto the bottom surface. For clarity the SiO.sub.2 layer 22 is shown as being of uniform thickness but, because of the various re-growing and etching steps it actually has a stepped appearance. The SiO.sub.2 layer 22 is commonly referred to as a passivation layer, because it protects the sensitive PN junctions and passivates them against the harmful effects of moisture and surface contaminants.
It is known that the maximum electric field for a particular voltage on a PN junction increases as the doping on either or both sides is increased; while in general the breakdown voltage of a junction depends on the bulk resistivity of the lightly doped side, junctions heavily doped on both sides are known to generate a substantial peak field even at modest applied voltages, since the space charge will spread in relation to the concentration on both sides. The main characteristic of an electric field is, of course, that it accelerates charge carriers (electrons or holes). As the reverse voltage across a junction increases the electric field increases and the carriers are accelerated more and more, until a point is reached where a single carrier colliding with a silicon atom causes a pair of carriers to be released. This pair itself is accelerated and the process of carrier generation continues until it results in avalanche breakdown of the junction. It is believed that the magnitude of the field and the distance over which it obtains are the main factors influencing the voltage at which avalanche breakdown will occur. It is clear, however, that lightly doped, high resistivity junctions create less of a field than heavily doped junctions, and are to be preferred in any high voltage device. Thus, typical high voltage devices are diffused into high resistivity silicon, even though they have other voltage-limiting problems.
Each junction 18, 20 in transistor 10 has its own associated BV. The voltage across the collector-base junction 18, with the emitter open, BV.sub.cbo, and the voltage from collector-to-emitter with the base open, BV.sub.ceo are important ones; breakdown across the base-emitter junction (BV.sub.ebo) invariably occurs at a lower level due primarily to the much heavier doping level in the base.
A factor that may be significant in affecting surface breakdown voltage is the behavior of doping atoms during various oxide growing steps inherent in the manufacturing process. Since surface boron incorporates more readily into SiO.sub.2 than into silicon, under oxide-growing conditions some boron is "leached" from the silicon surface into the growing oxide. Conversely, phosphorus segregates more readily into elemental silicon than into the growing oxide, so that as the oxide grows, phosphorus accumulates on the silicon side of the interface, the so-called "snowplow" effect. Thus the segregation coefficient to the impurity between the oxide and the silicon, and the time and temperature of the oxidation, all work to redistribute the impurities in the vicinity of the surface, modifying the bulk resistivity at the surface. The effect thereof under conditions of reverse bias may well be the creation of a lower voltage junction, collector to base, which breaks down at a much lower voltage than the bulk material would indicate.
The BV of a device can, of course, be increased by using a starting material having a higher bulk resistivity, but this is often to the detriment of other important parameters, such as frequency response and saturation level. As a result, the bulk of the effort to increase BV in silicon planar devices has been concentrated in the area of changing the surface characteristics of the material near the collector-base junction, in effect trying to block channels with so-called "guard rings" or "field relief rings". Some of these efforts are discussed below.
2. Prior Art
The foregoing is all well known to those skilled in the art and is presented herein in summary form only to provide the necessary basis for understanding of the present invention. A more detailed treatment of the subjects discussed may be found in many standard texts, such as Warner and Fodemwalt (Editors), Integrated Circuits, Motorola, Inc. Semiconductor Products Div. (1965). The particular problems associated with junctions under SiO.sub.2 films are treated by Atalla et al, Impurity Redistribution and Junction Formation in Silicon by Thermal Oxidation, Bell Systems Technical Journal, July 1960.
It is generally agreed that at the interface between a semiconductive body and the overlying oxide film, charges may be present or may be formed, which charges can move under the influence of an electric field. This is referred to as a surface charge. As a result of the presence of such surface charges, so-called "inversion layer" may be formed on the semiconductor surface below the insulating oxide. The inversion layer has a conductivity type opposite to the conductivity type of the underlying semiconductive material. It is believed that such an inversion layer not only reduces breakdown voltages but also, because it effectively increases PN junction surface area, increases capacitance, which is particularly undesirable in high frequency devices.
To remove or reduce these surface charges and inversion layers, a field relief ring may be employed. This is an annular metal layer placed over the insulating oxide layer at the area of the PN junction, which layer is connected to a reference potential (usually one side of the junction). Problems associated with field relief rings are that the rings should be fully enclosed, and they must be insulated from overlying conductives U.S. Pat. No. 3,491,273 of Stiegler discloses a field relief electrode.
A guard ring is a different approach to solving the same problem. A guard ring is in the semiconductive material and extends to the surface, but is spaced at a distance from the PN junction. The guard ring is generally of the same conductivity type as the underlying material, but has a significantly higher charge carrier concentration. Thus, if the bulk material is P-type, the guard ring would be designated P+. The concentration of charge carriers in the guard ring is sufficiently high so that an inversion layer on one side or the other thereof is interrupted. Drawbacks to this type of structure include the fact that they consume a lot of area, since if they are too close to the junction a low breakdown voltage (between the base material and the ring) will result. This is undesirable, particularly in integrated circuits.
Haenichen, U.S. Pat. No. 3,226,614 (1965) is typical of many patents in this area. Briefly, the base region is extended in a thin surface region having a higher resistivity than the bulk material on the base, thereby encouraging breakdown in the bulk rather than the surface. This intentional channel terminates in a ring of low resistivity material of the opposite conductivity type. This is alleged to prevent breakdown through induced channels. However, no figures are given on what BV.sub.cbo is achieved with this geometry.
In Tremere, U.S. Pat. No. 3,338,758 (1967) a PNP device is disclosed wherein a lightly doped out-diffused (P-) layer is provided across the entire surface, and a ring of P+ material is diffused around the N-type base, spaced therefrom by less than 2.mu.. This is alleged to produce a surface gradient protected high breakdown junction but, again, no BV.sub.cbo figures are given.
A more recent patent discloses in one instance the raising of the "effective" breakdown voltage of a silicon planar diode from 600 to 1100 volts, by the interposition of a ring containing "substitutionally active ions in interstitial positions." Martin et al, U.S. Pat. No. 3,515,956 (1970) employs ion implantation means to dope a very high resistance (9,000-11,000.OMEGA.-cm) N-type starting material. It is noted that any device employing such material could theoretically be expected to have a BV of thousands of volts. Such material is never used in conventional devices, however, because of the deleterious effect on other parameters. But the device disclosed by the patentee is by no means conventional, including as it does a junction 1/2 inch in diameter. The passivated device is first provided with the 1/2 inch P-type region of 0.01.OMEGA.-cm and then an even wider area is irradiated with 100 kilovolt boron ions to implant 10.sup.12 ions per cm.sup.2. Annealing follows. In one instance cited leakage current is reduced while BV is unaffected and in another case BV is raised to 1100 volts but leakage current is not affected. The former is attributed to an inversion layer and the latter to an accumulation layer, but why two different results are produced by the same process is not disclosed. The leakage currents reported are in the microampere range, some 3-4 orders of magnitude larger than can be tolerated in conventional devices, where such currents are normally measured in nanoamperes.
In considering this patent, it is to be noted that ion implantation produces interstitial impurities (i.e. impurities located within the crystal lattice between lattice sites), whereas diffusion produces substitutional impurities (i.e. impurities occupying lattice sites). Any interstitial atoms inherently strain a lattice, and lattice strain inherently increases leakage currents. Thus, the second irradiation mentioned at a lower level than the first, would appear to ameliorate the problems created by the first, in producing a gradually strained instead of a sharply strained lattice. Further, it is apparent that this treatment merely increases the resistance of the material, resulting in the same leakage current at a higher but still disappointing voltage, since BV for 9-11,000.OMEGA./cm N-type material should be several thousand volts.
While the present invention is concerned with planar rather than mesa technology, the patent of Blicher et al, U.S. Pat. No. 3,427,515 is of interest because of the concept of the symmetrical junction described therein. In particular, it is pointed out that in prior art high-voltage transistors the collector-base junction includes a collector region of very low impurity concentration and corresponding high resistivity, and a diffused base of high impurity concentration, so the junction is very abrupt. This produces a high electric field under conditions of reverse bias, and the junction breaks down readily. The patentees teach the formation by epitaxial rather than diffusion techniques of sub-regions of the junction, these base and collector regions having the same thickness and preferably the same concentration (a factor of 3 being the limit for concentration differences). This symmetrical junction exhibits a 50% lower field strength for a given reverse voltage, and the breakdown voltage is thus effectively doubled. As described by Blicher et al, the method is not applicable to planar devices.
British U.S. Pat. No. 1,153,495 of Lamming (1969) discloses a double-diffused base region adapted to overcome the so-called "base push-out" or "emitter dip" effect. Specifically, during emitter diffusion the collector-base junction is pushed farther into the collector region in the area below the emitter. This can give rise to poor electrical characteristics, particularly in high frequency planar transistors, where very narrow base widths are required. Starting with N-type silicon of 2 .times. 10.sup.15 donor concentration, the patentee first diffuses boron to a surface concentration of 2 .times. 10.sup.18 over a wide area which forms the junction at its periphery, and then diffuses boron over a smaller area to a surface concentration of 10.sup.20, the smaller area being surrounded by the larger area. Emitter diffusion follows, and has the effect of driving the second base zone into the first base zone below the emitter, but does not move the locus of the junction formed by the first zone. The patentee does not comment on BV.sub.cbo, but there are two reasons why this would be the same or lower than in conventional devices. At the high base impurity concentration disclosed (10.sup.20), it is necessary that the lower concentration zone be at least four orders of magnitude less for increased breakdown voltages to be observed. Further, in the area below the emitter where the second zone is disclosed as reaching the original junction, there will be a very steep concentration gradient, and this tends to lower BV.sub.cbo.
The recent patent of Davidsohn, U.S. Pat. No. 3,716,425 (1973), is also of interest in disclosing simplified diffusion masks which include adjacent tubs of single crystal silicon and the dielectric and matrix material therebetween.
While most of the prior art patents are devoid of actual figures for BV.sub.cbo under defined conditions, it is believed that highest voltage planar devices currently available are rated at about 300-400 volts, and such devices are sufficiently expensive to make their use uneconomical, except in military and space application.